IEEE

Design of an SoC Based on 32-bit RISC-V CPU and Lightweight Block Cipher PRINCE on FPGA

Abstract: This paper discusses an SoC consisting of the algorithm of PRINCE, a block cipher used in lightweight cryptography, and a 32-bit RISC-V CPU. The system was implemented successfully on an ...
IEEE

RISC-V-Based Evaluation and Strategy Exploration of MRAM Triple-Level Hybrid Cache Systems

Abstract: Magnetic random access memory (MRAM) is considered one of the most promising memories among nonvolatile memories (NVMs), to replace static random access memory (SRAM) in the computing system ...