Abstract: In this paper, a two-step Time-to-Digital converter (TDC) with a matching coarse-fine interface circuit for all-digital phase-locked loop (ADPLL) in a 40nm CMOS process is presented. A ...
Abstract: This brief presents a high gain frequency multiplier chain in 65-nm CMOS technology. The frequency doubler transistor interconnection layout is carefully designed to minimize the parasitic ...
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