IEEE

Ultra High Density 1D1R FinFET Dielectric RRAM in 5nm FinFET CMOS Logic Process

Abstract: An ultra-high density 5nm FinFET Dielectric (FinD RRAM) RRAM with 1D1R cross-point array is firstly developed with fully compatible 5nm FinFET CMOS Logic process and design rules. In this ...
IEEE

Design and Optimization of a Hybrid ALU Using CMOS, Pass Transistor Logic, and Transmission Gate Logic for Low-Power Applications

Abstract: This work presents the design and development of a hybrid Arithmetic Logic Unit (ALU) that combines the strengths of multiple logic families to achieve enhanced performance parameters. ALUs ...
GitHub

Example: ChaCha20‐Poly1305 for WireGuard

TODO top level IO streams and CSR inputs TODO diagrams TODO pipelines fsms TODO main file and data flow file modular to support designs that share encrypt components ...