EDN

Solido Design Launches New Process Variation Solution to Solve Well Proximity Effect Problems for Sub-90 nm Analog Designs

San Jose, Calif. – June 23, 2009 – Solido Design Automation, a leading developer of software for eliminating design loss caused by process variation in analog/mixed-signal and custom integrated ...
EDN

RC oscillator IP to counter effects of process variation

A new RC oscillator IP allows the frequency to be trimmed to remove the effects of process variation; it can also be configured as a free-running clock (FRC) where a high-accuracy clock is not ...
Semiconductor Engineering

Evaluation Of The Impact Of Source Drain epi Implementation On Logic Performance Using Combined Process And Circuit Simulation

The effect of low-k spacer thickness variation to select the best combination of spacer thickness and S/D epi shape to improve speed and power performance. In this paper, we explore an end-to-end ...
Semiconductor Engineering

Closing The Post-Silicon Timing Analysis Gap

Accurate static timing analysis is one of the most important steps in the development of advanced node semiconductor devices. Performance numbers are included in chip and system specifications from ...