EDN

Reusable architecture is DSP framework

Over a decade ago, fixed-point digital signal processor implementations became available, enabling easy software programmability for different DSP algorithms. Those early DSPs offered limited ...
Nasdaq

Synopsys Advances Processor IP Leadership with New ARC DSP IP Solutions for Low-Power Embedded SoCs

To address the broader range of power, performance and area (PPA) demands of embedded applications, Synopsys, Inc. (Nasdaq: SNPS) today announced it has expanded its DesignWare® ARC® Processor IP ...
Nasdaq

CEVA Unveils World's Most Powerful DSP Architecture

- Gen4 CEVA-XC architecture offers highest performance of 1,600 GOPS, innovative dynamic multithreading and advanced pipeline to reach operating speeds of 1.8GHz at 7nm - CEVA-XC16, first processor ...
ZDNet

Intel and Analog Devices ring in new DSP

Intel and Analog Devices Tuesday announced a new digital signal processor (DSP) architecture designed to pave the way for the next generation of mobile computing devices. Called Micro Signal ...
Electronic Design

Architecture Maps DSP Flow To Parallel Processing Platform

Programming parallel processors isn't easy, especially when the number of processing elements is large. No single technique applies to all situations. But in its Storm-1 architecture, Stream ...
Design-Reuse

Understanding the reuse of a DSP architecture for different designs (Ceva)

Eran Briman of CEVA describes reuse of a single DSP architecture for various applications and markets. As DSP usage becomes ubiquitous for voice compression and decompression, audio decoding and ...
Design-Reuse

icyflex: an ultra-low power DSP core for portable applications

The icyflex family of ultra low power 16/32-bit RISC processor cores developed by CSEM offers a flexible architecture that allows for different com-binations of control and DSP functionality. These ...
Electronic Design

Highly Parallel DSP Architecture Makes Quick Work Of Image-Processing Algorithms

The processor's SIMD portion enables one instruction to be simultaneously executed by a number (two, four, eight, or 16) of DSP processors called parallel datapath units. The CW4011 implementation ...
Business Insider

CEVA Announces Industry's First High Performance Sensor Hub DSP Architecture

MOUNTAIN VIEW, Calif., April 7, 2020 /PRNewswire/ -- CEVA, Inc. (NASDAQ: CEVA), the leading licensor of wireless connectivity and smart sensing technologies, today announced SensPro™, the industry's ...
Embedded

CEVA introduces new configurable sensor hub DSP architecture

In a world in which multiple sensors are being designed into almost everything, processing of all the data inputs, or sensor fusion, is becoming an increasingly important part of the system. To ...
ZDNet

Intel, Analog Devices ring in new DSP

Intel Corp. and Analog Devices Inc. Tuesday announced a new digital signal processor architecture designed to pave the way for the next generation of mobile computing devices. Called Micro Signal ...